In the manufacture of modern semiconductor integrated circuit memories, functional testing is not only used to screen defective memories from those that meet customer specifications, but also is often used in assisting the analysis of the cause of defective memories. For example, one may infer the cause of failure from the physical pattern of failed memory locations (e.g., single bits, single columns, single rows, pairs of bits, rows or columns). It is also known, particularly in the field of dynamic random access memories (dRAMs), to use the results of specific test sequences or patterns in making the inference of the cause of failures, for example as described in U.S. Pat. No. 4,642,784.
The use of functional test results to gather information regarding the cause of failure is especially beneficial when performed during functional probe test of the memories in wafer form, which is generally the first functional screen applied to the memories. The ability to infer the cause of failures from electrical probe test can either assist, or in some cases eliminate, the necessity for time-consuming and labor-intensive visual inspection of large numbers of failures. In addition, the efficiency with which expensive and scarce analytical resources such as scanning electron microscopy (SEM), Auger analysis and the like can be increased, as the electrical functional results can be used to identify those memories most appropriate for analysis using these tools. Furthermore, defect analysis based upon inferences from electrical functional test results has also greatly increased the amount of analysis data, as data may be acquired from each defective memory device, rather than only from a limited number of visually inspected samples. This increased sample size greatly improves the statistical accuracy of failure analysis, and enables automated statistical techniques to be applied for each manufacturing lot relative to a historical base line.
However, the ability and accuracy of these techniques to infer the true cause of a failing memory is limited, especially where many or all bits of the memory fail the test. This is because the comparison between actual output data received during the test and an expected data result merely indicates the result of the overall memory function, and does not indicate whether internal functional blocks of the memory, such as decoders, sense amplifiers, and the like, are operational.
By way of further background, many conventional logic devices such as microprocessors, application-specific integrated circuits (ASICs), and the like are tested by way of so-called scan testing. According to conventional scan testing, a serial path through the logic circuit is enabled in a special test mode, such that an input vector may be set on selected scan nodes in the device. The device is then operated for one or more operational cycles, and the states of the scan nodes are serially read out of the device. Comparison of the serial scan output with an expected output vector determines the functionality of the device, as well as data regarding the cause or location of failure, in some cases. However, due to the significant surface area constraints in the arrays of memory devices, such scan techniques are not at all suited for the testing and analysis of semiconductor memories.
It is an object of the present invention to provide a method and internal circuitry that directly indicates the operability of functional circuitry within a semiconductor memory.
It is a further object of the present invention to provide such a method and circuitry which can be realized in an efficient manner, relative to chip area.
It is a further object of the present invention to provide such a method and circuitry which does not affect the normal non-test mode operation and performance of the memory.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.